`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/11/07 10:58:03
// Design Name: 
// Module Name: mips
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mips (
    input wire clk,
    rst,
    output wire [31:0] pcF,
    input wire [31:0] instrF,
    output wire [3:0] memwriteM,
    output wire [31:0] aluoutM,
    writedataM,
    input wire [31:0] readdataM
);

  wire [5:0] opD, functD;
  wire [4:0] rtD;
  wire regdstE, alusrcE, branchD, regwriteE, regwriteM, regwriteW, alu_srca_pcE, write_reg_31E;
  wire [2:0] memtoregE, memtoregM, memtoregW;
  wire [5:0] alucontrolE;
  wire flushE, equalD;

  wire [31:0] srca2D, srcb2D;

  wire [1:0] hilo_enE, hiloreg_in_typeE;
  wire stallE;

  wire [1:0] jumpD;


  control_unit c (
      clk,
      rst,
      //decode stage
      opD,
      functD,
      rtD,
      branchD,
      srca2D,
      srcb2D,
      jumpD,

      //execute stage
      flushE,
      memtoregE,
      alusrcE,
      regdstE,
      regwriteE,
      alucontrolE,
      hilo_enE,
      hiloreg_in_typeE,
      stallE,
      alu_srca_pcE,
      write_reg_31E,
      //mem stage
      memtoregM,
      memwriteM,
      regwriteM,
      //write back stage
      memtoregW,
      regwriteW
  );
  datapath dp (
      clk,
      rst,
      //fetch stage
      pcF,
      instrF,
      //decode stage
      branchD,
      jumpD,
      srca2D,
      srcb2D,
      opD,
      functD,
      rtD,
      //execute stage
      memtoregE,
      alusrcE,
      regdstE,
      regwriteE,
      alucontrolE,
      flushE,
      hilo_enE,
      hiloreg_in_typeE,
      stallE,
      alu_srca_pcE,
      write_reg_31E,
      //mem stage
      memtoregM,
      regwriteM,
      aluoutM,
      writedataM,
      readdataM,
      //writeback stage
      memtoregW,
      regwriteW
  );

endmodule
